The present invention relates generally to vertex buffers and, more particularly, to the feeding vertex buffers with vertex data during processing in a graphics system pipeline.
Prior Art FIG. 1 illustrates a general system that implements a pipelined graphics processing system. In this system, data source 10 generates a stream of expanded vertices defining primitives. Each of such vertices has unique associated vertex attributes, or data. Prior Art Table A illustrates a non-exhaustive list of examples of typical vertex attributes.
Prior Art Table A
position(X Y Z W)
diffuse(R G B A)
specular(R G B F)
texture0(S T R Q)
texture1(S T R Q)
normal
Such vertices are passed one at a time, with the associated attributes through pipelined graphic system 12 via a vertex memory 13 for storage purposes. Once received from the vertex memory 13 into the pipelined graphic system 12, the expanded vertices are transformed by a transformation module 14, lit by a lighting module 16, and further clipped and set-up for being rendered by a rasterizer 18, thus generating rendered primitives that are then displayed on display device 20.
During operation, the transform module 14 may be used to perform scaling, rotation, and projection of a set of three dimensional vertices from their local or model coordinates to the two dimensional window that will be used to display the rendered object. The lighting module 16 sets the color and appearance of a vertex based on various lighting schemes, light locations, ambient light levels, materials, and so forth. The rasterization module 18 rasterizes or renders vertices that have previously been transformed and/or lit. The rasterization module 18 renders the object to a rendering target which can be a display device or intermediate hardware or software structure that in turn moves the rendered data to a display device.
Upon receiving a vertex, each of the foregoing modules requires a predetermined amount of time before being able to output the processed vertex and receive an additional vertex. Initially, this delay is handled by temporarily storing the vertex in the vertex memory 13. Conventionally, the vertex memory 13 is responsible merely for storing the attributes of the vertices to be processed, and fails to handle any information relating to a manner in which the attributes of the vertices are to be processed.
In prior art systems, the vertex memory 13 stores vertices received from the data source 10 in a first in first out (FIFO) sequence. In operation, the attributes, i.e. position, diffuse, etc., of a first vertex are received in the FIFO sequence. Prior to loading attributes of a second vertex, all of the attributes of the first vertex traditionally must be outputted, or xe2x80x9cdrained.xe2x80x9d For a vertex buffer with five slots, it may therefore require up to five drain operations, or xe2x80x9cstalls,xe2x80x9d before the attributes of the second vertex may be loaded. This is often a considerable source of delay.
FIG. 1A illustrates one technique of mitigating such delay. As shown, two vertex attribute buffers 22, 24 may be coupled in tandem between the data source 10 and the remaining graphics processing pipeline. During use, the first vertex attribute buffer 22 may be completely filled with the attributes of the first vertex. Immediately upon the first vertex attribute buffer 22 being filled, the attributes may be copied to the second vertex attribute buffer 24. This immediately frees the first vertex attribute buffer 22, thus making it capable of receiving the attributes of the second vertex without the five stalls.
While the technique of Prior Art FIG. 1A may be seem to render an adequate solution, the use of the two vertex attribute buffers 22, 24 unfortunately requires additional space on an associated integrated circuit. Further, a large copy operation is still necessary which incurs undesirable delay.
A method, apparatus and article of manufacture are provided for managing vertex data in a vertex buffer. First, vertex data is received and stored in the vertex buffer. Thereafter, the vertex data is outputted from the vertex buffer to a processing module. During operation, a plurality of command bits is passed from the vertex buffer for determining a manner in which the vertex data is inputted and processed in the input buffer of the processing module. Such command bits are received from a command bit source. Further, a plurality of mode bits indicative of a status of a plurality of modes of process operations is passed. Such mode bits are received from a mode bit source. The mode bits are adapted for determining a manner in which the vertex data is processed in the processing module.
In one embodiment of the present invention, a particular method may be employed for efficiently draining and loading the vertex attribute buffer during graphics processing. Initially, at least one set of vertex attributes is received in a vertex attribute buffer for processing. Each set of vertex attributes includes a plurality of vertex attributes corresponding to a single vertex. In use, the vertex attributes are stored in the vertex attribute buffer upon the receipt thereof. Further, each set of stored vertex attributes is transferred to a corresponding input buffer of a processing module in a predetermined order.
Additionally, the received set of vertex attributes may be monitored in order to determine whether a received vertex attribute has a corresponding vertex attribute of a different set currently stored in the vertex attribute buffer. Upon it being determined that a stored vertex attribute corresponds to the received vertex attribute, the stored vertex attribute is immediately outputted to the corresponding input buffer of the processing module out of order, thus allowing the incoming vertex attribute to take its place.
This technique avoids the delay often incurred during traditional buffer loading and draining methods. There is no need to drain the entire vertex attribute buffer before loading vertex attributes of another vertex. Further, the use of additional vertex attribute buffers for copying purposes is avoided.
These and other advantages of the present invention will become apparent upon reading the following detailed description and studying the various figures of the drawings.